Field of the Invention
The invention relates to reliability of a NAND (not AND) type or NOR (not OR) type flash memory, and particularly relates to an erasing method of a flash memory with less reliability deterioration even if programming and erasing operations are repeatedly performed.
Description of Related Art
FIG. 1 is a schematic cross-sectional view of a cell array of a NAND-type flash memory. An N-well 12 is formed in a P-type silicon substrate 10, and a P-well 14 is formed in the N-well 12. A plurality of transistors constructing a NAND string is formed in the P-well 14. One NAND string includes a plurality of memory cells connected in series, a source line selection transistor connected to an end of the memory cells, and a bit line selection transistor connected to another end of the memory cells. In FIG. 1, a plurality of memory cells 20 connected in series, a source line selection transistor 22, and a bit line selection transistor 24 are illustrated. A plurality of such NAND strings is formed in the P-well 14 along a row direction, and the NAND strings in one P-well 14 construct one block.
A source line SL is electrically connected to an n-diffusion region (a source region) 23 of the source line selection transistor 22, and a bit line BL is electrically connected to an n-diffusion region (a drain region) 23 of the bit line selection transistor 24. Moreover, a p+ diffusion region 26 for a contact is formed in the P-well 14, and an n+ diffusion region 27 is formed in the N-well 12, and the two diffusion regions 26 and 27 are connected through a contact 28 commonly used by the N-well/P-well. According to following description, when an erasing operation is to be performed to a selected block, an erasing pulse of a high voltage of the P-well is applied through the commonly used contact 28.
FIG. 2 is an equivalent circuit diagram of a cell array of a NAND-type flash memory. As shown in FIG. 2, a plurality of word lines WL1, WL2, . . . , WLn is formed along a row direction intersected with the NAND strings, and each of the word lines WL is commonly connected to control gates of the corresponding memory cells 20 in the row direction. A selection gate line SGS is commonly connected to gates of the source line selection transistors 22 in the row direction, and a selection gate line SGD is commonly connected to gates of the bit line selection transistors 24 in the row direction. When the source line selection transistors 22 are turned on through the selection gate line SGS, the NAND strings are electrically connected to the source line SL, and when the bit line selection transistors 24 are turned on through the selection gate line SGD, the NAND strings are electrically connected to the bit line BL.
FIG. 3 is a diagram illustrating voltage waveforms of nodes in an erasing selected block of the NAND-type flash memory when an erasing pulse is applied. A node N1 represents the contact 28 commonly used by the N-well/P-well, a node N2 represents the diffusion region 23 used by the contact of the source line SL, a node N3 represents a gate of the source line selection transistor 22, a node N4 represents a word line (control gates) of the memory cells 20 in a same block, a node N5 represents a gate of the bit line selection transistor 24, and a node N6 represents a waveform of the diffusion region 23 used by the contact of the bit line BL. Moreover, in a non-selected block, the node N4 has the same voltage waveform with that of the node N3 or N5 in the erasing selected block.
In the NAND-type flash memory, data is erased block by block. At this time, the word line of the selected block is set to 0V or a voltage lower than that of the P-well 14, and an erasing pulse Ps of a strip-type positive voltage is applied to the P-well 14 that forms the memory cell array, and after the erasing pulse Ps is applied, the potential of the P-well 14 is restored to 0V. At this time, the voltage of each of the nodes N2, N3, N5 and N6 is automatically boosted through capacitance coupling with the P-well 14. After the erasing operation, it is determined whether threshold values of the memory cells in the selected block are below a certain value through verification read out. If the threshold values of all of the memory cells in the block are below the certain value, the erasing operation is completed, and if the threshold values of a part of the memory cells are above the certain value, the erasing pulse Ps is again applied to again perform the verification read out (for example, a patent literature 1).
Moreover, in order to control a lower limit of a threshold distribution amplitude of the erased memory cells, soft programming is performed to the erased memory cells, and soft programming verification is performed (for example, a patent literature 2). The above flow is shown in FIG. 4, as shown in FIG. 4, following control is implemented: an erasing pulse Ps is applied in order to erase data of the selected memory cells (step S10). Then, erasing verification is executed for verifying whether an upper limit of threshold values of the memory cells is below a fixed value (S20), and if it is verified to be success in the erasing verification, the soft programming verification is executed for verifying whether a lower limit of the threshold values of the memory cells is above a fixed value (S40). Soft programming is executed to the memory cells failed in the soft programming verification (S30), such that the lower limit of the threshold distribution amplitude is above the fixed value.
On the other hand, during a writing (programming) operation, the P-well 14 is set to 0V, and a high voltage is applied to the selected word line. The bit line BL is applied with 0V or a positive potential, and in case of 0V, a silicon surface of the selected memory cell is 0V, and a tunnel current of electrons flows from the silicon substrate towards a floating gate. Therefore, the threshold value of the memory cell becomes higher than a certain specified value.
Patent literature 1: Japan Patent Publication No. 2012-027979
Patent literature 2: Japan Patent Publication No. 2007102923
In the past flash memories such as the NAND-type flash memory, if an erasing/programming (data rewriting) operation is repeatedly performed, performance of an oxide film under the floating gate is deteriorated, such that a conductance (Gm) is deteriorated due to trapping of holes/electrons of the oxide film. Moreover, a data retention characteristic is aggravated. Therefore, data rewriting times is limited, and when the data rewriting times is above the limitation, reliability of the flash memory can not be guaranteed.
Factors that cause the oxide film deterioration are plural, and it is known that during a period of applying the erasing pulse to the P-well till applying a programming pulse, the oxide film deterioration exists. By changing an interval of applying the erasing pulse to the P-well till applying the programming pulse to the word line to repeatedly rewrite data, an experiment result of measuring an I-V characteristic of the memory cell in the programming state is shown in FIG. 5(a). To be specific, regarding the interval from erasing to programming, three intervals of 0.05 second (▴), 0.5 second (▪) and 5 seconds (●) are provided to compare the I-V characteristic of the memory cell when the number of programming/erasing (P/E) cycles is 1000 and the I-V characteristic of the initial, un-programmed and fresh memory cell. According to the experiment result, it is known that the smaller the interval is, the more the I-V characteristic of the repeatedly programmed/erased memory cell being closed to the I-V characteristic of the initial and fresh memory cell. In other words, the larger the interval is, the larger the I-V characteristic deviates, and the larger the deterioration of the conductance Gm is.
FIG. 5(b) is a graph showing a relationship between the number of P/E cycles and shift amounts of the threshold values of the memory cells, in which a horizontal axis represents the number of P/E cycles, and a vertical axis represents the shift amounts of the threshold values Vth of the memory cells, and according to the experiment result, the shift amount of the memory cell with the smallest interval (0.05 second) is the smallest, and the shift amount is increased as the interval is increased. Namely, it is known that the greater the interval of the memory cell is, the higher a trapping energy level of the silicon interface is, and therefore the less a potential dependency of the control gate of the I-V characteristic is, which is regarded as the oxide film deterioration caused by placement after the erasing pulse is applied, and the oxide film deterioration may aggravate reliability of the subtle memory cells to cause reduction of data rewriting times with guaranteed reliability.
FIG. 6 is a graph showing influences on deterioration of the conductance Gm caused by an interval Tp_e from programming to erasing and an interval Te_p from erasing to programming, in which a horizontal axis represents the number of P/E cycles, and a vertical axis represents a variation proportion relative to a drain current flowing through the initial memory cell. Moreover, ▴ represents a situation that the interval Tp_e and the interval Te_p are all short, ● represents a situation that the interval Tp_e is long and the interval Te_p is short, and ▪ represents a situation that the interval Tp_e and the interval Te_p are all long. When the number of the P/E cycles reaches 1000, the memory cell with the short interval Tp_e and the short interval Te_p has the smallest conductance deterioration, the memory cell with the long interval Tp_e and the short interval Te_p has the second smallest conductance deterioration, and the memory cell with the long interval Tp_e and the long interval Te_p has the largest conductance deterioration. Here, in the memory cell with the short interval Te_p (▴ and ●), the conductance deterioration nearly has no difference, so that the interval Tp_e does not has a great influence on the conductance deterioration. Namely, compared to the interval Tp_e, the interval Te_p has a larger influence on the oxide film deterioration. In other words, compared to a placing time of the memory cells after the programming operation, a placing time of the memory cells after the erasing operation may cause larger influence on the oxide film deterioration, and compared to the electrons, the holes more dominate deterioration of the tunnel oxide film.
FIG. 7 is a cross-sectional view of a memory cell applied with the erasing pulse Ps, and FIG. 8 is a band diagram between the floating gate and the silicon substrate when the erasing pulse is applied. As shown in FIG. 7, when a voltage of 0V is applied to a control gate 30, the erasing pulse Ps is applied to the P-well 14, and a high voltage is applied to a tunnel oxide film 34 located right below a floating gate 32, the electrons flow from the floating gate 32 to the silicon substrate based on an FN tunneling effect. As a result, when the erasing operation is ended, the floating gate 32 carries positive charges. As shown in FIG. 8, the electrons reaching the silicon substrate have high energy to produce holes with high energy, and a part of the holes is injected into the oxide film 34.
FIG. 9 is a band diagram of the memory cell applied with the erasing pulse when the threshold value thereof is below 0V. Regarding the holes injected into the oxide film 34 when the erasing pulse is applied, if the floating gate 32 carries the positive charges when the P-well 14 is set to 0V, the floating gate 32 has a positive potential relative to the silicon surface due to the positive charges. Therefore, the holes in the oxide film 34 slowly move toward the silicon substrate due to a self electric field in the oxide film (the Pool-Frenkel current). A part of the holes reaching the silicon interface is trapped by the oxide film to form an interface energy level. During read verification, the P-well is fixed to 0V, the word line becomes 0V or a certain positive potential, and the phenomenon that the holes move towards the silicon substrate is not changed. Therefore, in the past erasing method, during the period after the erasing pulse is applied, the holes move towards the silicon interface to form the interface energy level.